CMOS-IC Design Director

Core Responsibilities: 1. Lead architecture and design of high-channel-count CMOS MEA recording and stimulation chips. 2. Define long-term IC architecture, technology roadmaps, and scalability strategies for next-generation neural interfaces 3. Design low-noise, low-power analog front ends for neural recording. 4. Define scalable readout architectures for ultra-high channel-count systems. 5. Coordinate IC design decisions with system-level constraints including signal integrity, power, bandwidth, and thermal limits. 6. Lead full IC development cycles, including schematic design, layout oversight, verification, tape-out, and foundry engagement. Qualifications & Requirements: 1. MS or PhD in Electrical Engineering, Microelectronics, or related field. 2. Strong background in analog and mixed-signal IC design. 3. Experience with large-scale ADCs, on-chip signal processing, and large-scale sensor interfaces. 4. Multiple successful silicon tape-outs with demonstrated ownership of key blocks or full-chip architecture. 5. Ability to work full time and closely with an interdisciplinary team.